Demands for high-speed data communication continue to push the electronics industry to develop faster and higher-functioning circuits, as has been realized in very-large-scale integration of circuits on small areas of silicon wafer. These complex circuits are often implemented as functionally-defined modules that operate to manipulate data presented for such high-speed transmission. The transmitted data can be passed in small or large amounts of data sets from these functionally-defined modules to various end points including, for example, a node dedicated to receive and process the data sets and a semi-open environment (such as a wired data bus) that provides access to one or more different nodes.
Whether these functionally-defined modules are implemented as stand-alone chips or in combination with other circuit arrangements (e.g., systems or subsystems), many applications for high-speed data communication are benefited by proper alignment of data, especially at the receiving end where the data is typically assembled for subsequent use. Data that is improperly aligned at the receiving end can present a data integrity issue that would typically require extraneous and time-consuming processing and/or unintelligible data.
The speed at which a given amount of data can be passed between two such communication nodes is referred to as “throughput.” Many high-speed communication applications increase throughput by using parallel data transmission in which multiple data bits are simultaneously sent across parallel communication links. As an example of this approach, one such parallel-communication system would separate the data in each set for loading into transmission-link drivers that feed the loaded data onto respective parallel communication links. In this context, the parallel communication links carry the data from the respective transmission-link drivers to respective link receivers for reassembly of the separated data into the original data sets.
In some applications, the channel includes a separately-transmitted signal (such as a reference clock) to the transitions over the parallel signal lines leaving the sending module in a synchronous relationship with each other and/or to the clock on the sending module. At the other end of the parallel data interconnect, the data is received along with a clock signal; the receive clock is typically derived from or is synchronous with the clock on the sending module. The rate at which the data is passed over the parallel signal lines is sometimes referred to as the (parallel) “bus rate.”
In such systems, proper data recovery is typically obtained by ensuring that the signals received over each communication link (which signals represent the transmitted data) have a specific phase relationship relative to the intended phases of data carried by the other links. Systems designed to communicate data at relatively high speeds are often designed to allow for a certain amount of “skew” from the time at which the parallel data is transmitted and the time at which the data signals are received. There are many sources of skew including, for example, transmission delays inherently introduced in each line due to impedance factors, circuit variations and signal delays in the I/O (input/output) drivers and receivers, and intersymbol interference. Typically, the potential for this undesirable skew increases with increases in line transmission rate.
Programmable devices are a class of general-purpose integrated circuits that, when configured for such high-speed data transmission applications, can present an accentuated potential for skewed data. Such programmable devices, whether mask programmable or field programmable, can be classified as programmable memory devices or programmable logic devices. Field programmable gate arrays (FPGA) have become very popular for telecommunication applications, Internet applications, switching applications, routing applications, et cetera. Generally, an FPGA includes a programmable logic fabric and a programmable input/output section. The programmable logic fabric may be programmed to perform a wide variety of functions corresponding to the particular end-user applications. The programmable input/output section provides the high-speed data transmission.
The programmable input/output section is fabricated on the perimeter of a substrate supporting the FPGA and provides coupling to the pins of the integrated circuit package allowing users access to the programmable logic fabric. Typically, the programmable input/output section includes a number of serial/deserial transceivers to provide access to the programmable logic fabric. Such transceivers include a receiver section that receives incoming serial data and converts it into parallel data and a transmitter section that converts outgoing parallel data into an outgoing serial data stream.
The transceivers of the I/O section often use a different clock domain than the programmable logic fabric. As the speed of the incoming and outgoing serial data increases well into the gigabit-per-second range, the separate clock domains of the input/output section and the programmable logic fabric can present a synchronization problem between the two sections that, in turn, can cause corruption of data.
One approach for addressing this issue is to rely on a reset-signal in each serial line of a channel-bonded set to set the phase of the clock divider circuit. Due to the large distance between the serializer/deserializer (SerDes) transceivers that are typically used to communicate a channel-bonded data, and a synchronization of the reset-signal to the local high-speed clock, the best phase alignment that can be accomplished is plus or minus two clock cycles.
For many present and future applications involving programmable devices and other types of skew-susceptible parallel transmission arrangements, with regard to its integrity and/or overall throughput, data communication can benefit from different phase alignment approaches.